Electrostatic discharge (ESD) may cause damage to semiconductor devices on an integrated circuit during handling of the integrated circuit chip package. Prevention of such damage generally is provided by protection circuits incorporated into the chip of the integrated circuit. In general, such protection circuits include a switch that is capable of conducting relatively large currents during an ESD event. Various devices such as a Silicon Controlled Rectifier (SCR) can be utilized to provide the switching function required to essentially shunt the protected circuitry during an ESD event. Previous circuits and structures used for ESD protection can withstand high levels of ESD stress. However, recent advances in technology have produced devices which can fail at voltage levels lower than the triggering voltages of prior art protection circuits.
SCR protection devices that use a gate electrode to lower their trigger voltages are shown in FIGS. 1a and 1b. These protection devices are gated SCR structures 10 having a polysilicon gate 12 connected to ground. SCR structures 10 comprise a p+ region 16, an n+ region 18, both of which are located in an n-well 20, an n+ region 24 located in the p-substrate 30 and polysilicon gate 12. The gate electrode 12 is separated from the silicon regions below it by a thin (.about.50.ANG.-200.ANG.) oxide layer 32. In FIG. 1a, gate electrode 12 extends onto an adjacent field oxide region, whereas in FIG. 1b it does not. Typically, p+ region 16 and n+ region 18 are electrically connected and form one terminal of the device 14 connected to the input/output bond pad. The gate 12 and the n+ region 24 are connected together and form the other terminal 22 which is usually connected to ground. The p-substrate 30 may also be connected to ground, depending on the application. When an excess voltage appears at the terminal 14, the presence of the thin oxide 32 and the gate 12 raises the electric field in response to which the device will begin to conduct current at a lower voltage level than the triggering voltage of a typical SCR without the gate and the thin oxide. The current triggers SCR structure 10 to a low-impedance state, which, in turn, dissipates the ESD event. Polysilicon gate 12 connected to ground thus reduces the triggering voltage of a typical SCR structure from about 50 volts to about 24 volts for the structure of FIG. 1a and to about 15 V for the structure of FIG. 1b. Unfortunately, an even lower trigger voltage is required for many of today's more advanced circuits.
Another protection device having a low triggering voltage is shown in FIG. 2. FIG. 2 illustrates a large nMOS transistor 40 having its gate tied through a resistor 42 to ground 44. The drain of the nMOS transistor 40 is connected to output pad 46 and the source is connected to ground 44. Output pad 46 is also connected to internal circuitry 48. Inherent in the structure of nMOS transistor 40 are two parasitic capacitances 50 and 52. During normal operation, transistor 40 is non-conducting. However, when an excess voltage appears at pad 46, parasitic capacitor 50 will also bump up the voltage at the gate of nMOS transistor 50. When the voltage at the gate exceeds the turn-on voltage of transistor 40, transistor 40 will begin to conduct and discharge the excess voltage, thereby protecting internal circuitry 48. Resistor 42 allows the voltage at the gate to relax back to ground in a given amount of time determined by the product of the resistor 42 and capacitor 52 and the ratio of the parasitic capacitances 50 and 52.
Although transistor 40 can be designed to trigger at a sufficiently low voltage, there are two disadvantages in using this type of protection device. The first disadvantage is area. In order to dissipate sufficient amounts of energy, transistor 40 must be large (e.g., on the order of ten thousand square microns). A second disadvantage of transistor 40 is that it adds significant capacitance to that which must be driven by the internal circuitry. A third disadvantage of transistor 40 is that an nMOS transistor heats up more than an SCR. Hence, it is not able to withstand as severe an ESD stress in comparison to an SCR device. Accordingly, there is a need for a protection device that has a low triggering voltage, low input capacitance, and that requires a small area.